Conventional programmable logic devices, such a field programmable gate arrays (FPGAs), are configured in response to a configuration bitstream. The configuration bitstream is typically shifted into the programmable logic device, and then loaded into an array of configuration memory cells. The programmable logic device is configured in response to the contents of the configuration memory cells. An exemplary configuration process for an FPGA is described in “Virtex Series Configuration Architecture User Guide,” Xilinx Application Note XAPP151 (Ver. 1.7), published October 2004.
In some cases, a configuration bitstream can include 20 million or more configuration data bits. As a result, a large external memory is required to store the configuration bitstream. In addition, it takes a relatively long time to load such a large bitstream. For example, it may take about 400 milliseconds to load a configuration bitstream having 20 million configuration data bits.
Normal compression algorithms may be used to reduce the required number of configuration data bits. One compression algorithm that has been used to compress configuration bitstreams is the Lempel-Ziv (LZ) compression algorithm. The LZ compression algorithm operates efficiently in applications where groups of symbols occur frequently. However, these compression algorithms typically only reduce the required number of configuration data bits by a factor of two. Moreover, use of such a compression scheme requires additional decompression logic either in the FPGA itself or coupled to the FPGA.
In some programmable logic devices, the configuration bitstream is divided into subsets called frames. Inside the programmable logic device, a complete frame is buffered and written into configuration memory cells at a frame address. In a typical configuration process, frame data is transmitted to the programmable logic device serially and when each frame has been completely received, configuration control logic writes the data to the next frame address location. Some programmable logic devices include a “multi-frame write” capability as part of the configuration logic. The multi-frame write capability permits the configuration logic to write the buffered frame bits to multiple addresses in its configuration memory. Thus, the configuration data stream includes the frame addresses for duplicate frames, rather than the duplicate frame data. This capability permits the configuration data to be compressed, but only if complete frames are identical (i.e., every bit of one frame has the same logic value of every corresponding bit in another frame). However, complete data frames are not often identical, since different parts of the programmable logic device perform different functions. As such, compression using multi-frame write provides only a small amount of data compression, if any.
Accordingly, there exists a need in the art for an improved bitstream compression technique for a programmable logic device that does not require additional decompression hardware.